Comments on: Who ordered sequential consistency?

By: C++ atomics and memory ordering « Bartosz Milewski’s Programming Cafe

Mon, 01 Dec 2008 22:01:45 +0000

[...] are some other algorithms, like the Peterson lock, which do require memory fences on the x86 (see my previous post). So it’s not just the matter of skipping all [...]

By: Anthony Williams

Anthony Williams — Fri, 28 Nov 2008 13:13:52 +0000

The x86 has one of the least-relaxed memory models of common processors. The POWER memory model and Sun SPARC RMO memory model give the processor(s) much more freedom to reorder operations, and this freedom is reflected in the C++0x memory model.

There are some examples in my recent blog entry on the C++0x memory model:

http://www.justsoftwaresolutions.co.uk/threading/memory_models_and_synchronization.html

By: Dmitriy V'jukov

Dmitriy V'jukov — Fri, 14 Nov 2008 12:00:31 +0000

I think it was 3 or 4 years of just reading/studying/thinking, and only about 1.5 years of active discussions.
Definitely it’s extremely hard stuff… at the beginning. I just wanted to show what it’s all about. I.e. it’s hard, but what one can get if he masters it?
And another interesting consequence is that such low-level details as memory ordering, cache behavior, etc also can give many insights into such things as systems architecture, distributed systems, etc.

By: Bartosz Milewski

Bartosz Milewski — Fri, 14 Nov 2008 00:29:14 +0000

Dmitriy, I have come across your posts in several newsgroups. Let’s face it, you are one of the very few specialists in this area who know what they are talking about. Please tell the readers how many years you have dedicated to studying concurrency and reading and discussing processor specs. I will then say: Anybody with that much experience feel free to play games with memory fences.

By: Dmitriy V'jukov

Dmitriy V'jukov — Thu, 13 Nov 2008 20:02:58 +0000

Well, one can stay away form such games if it’s Ok for him to have 100x performance degradation.

As an example one can take a look on this hash map implementation:
http://groups.google.com/group/lock-free/browse_frm/thread/a826061a4af06dc0
It’s 50x faster that Intel Threading Building Blocks concurrent_hash_map already on quad-core. TBB’s hash map indeed uses ’sequential consistency’ to simplify things a bit.

Also one can use tools like Relacy Race Detector:
http://groups.google.com/group/relacy
to kick $hit from algorithms like Peterson’s mutex etc. Relacy Race Detector nearly 100% models C++0x’s extremely relaxed memory model. So it can compromise algorithm which fails only on, for example, platforms with non Total Store Order (I believe that most current x86 are actually TSO).